1. Field of the Invention
The present invention relates to methods for manufacturing structures of semiconductor regions on insulator.
The present invention is described hereafter in relation with the integration of a MOS transistor.
2. Discussion of the Related Art
FIG. 1 illustrates, in partial simplified cross-section view, the structure of a MOS transistor formed in a conventional silicon-on-insulator (SOI) region.
The transistor comprises an insulated gate G laid on a portion of a silicon substrate 2 on insulator of a first conductivity type, for example, P. More specifically, the portion of substrate 2 in which the transistor is formed is defined by vertical insulation areas 3 of shallow trench insulation (STI) type. Substrate 2 and trenches 3 rest upon an insulating layer 4 of a uniform thickness T that separates them from a semiconductor wafer 6. Source/drain regions 8 extend, at the surface of substrate 2, on either side of insulating spacers 10 formed around gate G.
The selection of the value of thickness T of insulator 4 interposed between wafer 6 and substrate 2 is a problem.
On the one hand, under source/drain regions 8, any capacitive coupling with wafer 6 should be reduced to a minimum. The value of thickness T of insulator 4 must thus be high.
On the other hand, when thickness T of insulator 4 increases, malfunctions linked to known so-called “short channel” effects can be observed. Such effects are linked to the channeling of the field lines in an insulator. Thickness T thus has to be limited to relatively low values.
For devices having a reduced length L of gate G, that is, smaller than 100 nm, value T is thus currently selected between 200 and 400 nm. However, this is only a compromise between two opposite constraints.
The above-described problems significantly increase as the component dimensions, especially gate length L and the thickness of substrate 2, decrease.